One day after the presentation of the new generation of AMD graphics cards , the Radeon RX 6000 based on the Navi 2x architecture colloquially known as Big Navi, have reappeared in references about one of the innovations in terms of architecture that they would have these new GPUs compared to the first generation RDNAs, the Infinity Cache .
If a few days ago we had a possible confirmation in the form of a registered trademark, now we have the final confirmation of the implementation of Infinity Cache in the next Radeon graphics cards through the drivers, which give us a series of additional data about one of the changes from RDNA 2 to RDNA most important at the architectural level.
References to the Infinity Cache in the drivers
Through the Linux drivers for the new generation of AMD GPUs, it has been possible to confirm the physical existence of the Infinity Cache, specifically in relation to memory access at the last level or MALL that was leaked days ago.
The information that can be gleaned from these drivers is that the RX 6000’s top-of-the-range GPU, codenamed Navi 21 or Sienna Cichlid, would have a total of 128MB of Infinity Cache, which is consistent with rumors that have been been appearing in recent weeks regarding this type of memory.
The reference in the driver is regarding the display controller, Display Core Next on AMD GPUs, which is the unit that reads the final image buffer and sends it to the screen through the Display Port or HDMI interfaces. In this case it refers to the DCN’s ability to access the Infinity Cache and with this we can draw a series of conclusions in advance about the RX 6000.
The Infinity Cache would be a top-level cache
There are three reasons that would confirm it:
- The concept «Access to memory at the last level», called MALL, which already gives us a clue about the nature of the Infinity Cache.
- The second is that the caches in every processor regardless of whether it is a CPU, a GPU, or any other type of processing unit increase its storage capacity compared to previous levels.
- The display controller’s access to this cache, which means that we are facing the cache with the highest level of global access within the GPU.
To understand the last point, it must be taken into account that GPUs in general are divided into two different parts, which are linked through a common north bridge:
- The core part of the GPU tasked with rendering 3D graphics or doing heavy computing tasks, AMD calls it GFX in its graphics architectures.
- The second block is a series of support processors that perform other tasks such as communication with the system’s main RAM, video encoding and decoding, and sending images to the screen.
Well, that series of support processors do not have access to any of the caches of the central part of the GPU which AMD calls GFX, which indicates that the Infinity Cache in the RX 6000 would be in the north bridge, which is the common part between the support processors and the GFX, and it would be a cache that would be at a level above L2, so this is a last level cache or Last Level Caché.
The Infinity Cache on the RX 6000 is a legacy of Zen architecture
In Zen architecture, the highest level cache and therefore the last one in the hierarchy is L3, what we call a “Victim Cache”, and this means that when a data does not fit in the L2 cache instead of dumping it to memory what it does is dump it to L3 in case it has to be recovered later, so all the data that is the victim of a discard ends up in the L3 cache.
In the case of the Infinity Cache, we would also be facing a Victim Cache, but in that case, its application has to do with the so-called Tile Caching that has been adopted in AMD and NVIDIA GPUs for years where the image is resolved by tiles while these will fit in the cache, but if they do not fit then they are resolved in main memory, which causes a much higher consumption per instruction due to the remoteness of the data.
AMD calls this concept “Draw Stream Binning Rasterizer” or DSBR and is implemented in its graphics architecture from Vega onwards.
The idea of adding the Infinity Cache is therefore to ensure that a large amount of data does not fall into the GDDR6 and is kept in cache, since the fact that a data is closer to its place of processing translates into consumption lower and, therefore, we can deduce that the Infinity Cache is key to the Big Navi architecture when it comes to achieving high clock speeds.
Remember that this Wednesday, October 28 is the presentation of the Radeon RX 6000 and we will definitely leave doubts about this implementation of the Infinity Cache in the Radeon RX 6000 graphics, but the drivers have already given us an almost exact idea of it.
Source> FreeDesktop (patch source code)