From Germany come leaks around the performance of the AMD EPYC MILAN CPUs, which are expected to be the first CPUs with the Zen3 microarchitecture to hit the market. As indicated, the 7nm manufacturing process, the same maximum number of cores (64), the use of DDR4 memory, and the PCI-Express 4.0 interface are maintained.
The novelties are changes in the structure of the Core Compute Die (CCD) and, therefore, of the Core Compute Complex (CCX). Each of the current CCDs consists of two CCX clusters in which the L3 cache is divided into two 16MB caches. With MILAN this cache will not be divided, so it comes in the form of a single 32 MB cache. AMD itself had mentioned integrating more than 32 MB in October, so it apparently has not reached more than 32 MB. The number of nuclei is identical to eight per CCD, but the CCX clusters in their former form no longer exist.
The data also provides performance values: these speak of a +15 percent CPI-related performance increase for entire workloads. For EPYC processors with up to 32 cores, AMD wants to achieve a performance increase of +20 percent compared to ROME processors with Zen2 cores; single thread performance should also increase by +20 percent . For the largest EPYC processors with up to 64 cores, AMD expects a performance increase of around 10 to 15 percent .
Apparently, AMD can achieve a higher clock frequency for processors with fewer cores, so that the increase in performance has a correspondingly greater effect with fewer cores. So far this is not surprising, as it is the expected performance improvement since practically the beginning of the year.
If we want a bigger performance leap, we will have to wait for the AMD EPYC GENOVA , where Zen4 @ 5nm with TDPs from 120 to 240W , DDR5 memory and PCI-Express 5.0 interface would come into play , which would arrive at the end of 2021.